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How to Model Frequency to Voltage Converter(FVC) with Verilog-A?

Teem

Dear All:

    I am trying to model the frequency to voltage converter(FVC) using verilog-A. The  function of FVC is simply to convert the input frequency to the corresponding output voltage. Mathematical expression in time domain is Vout=1/Fin * (1 - R^t), where R is a constant smaller than one.

    My input to FVC is phase(Phi-in), thus I need to take derivative of the input to convert to frequency, that is, Fin=ddt(Phi-in). Several things baffled me then,

    1.Strang thing is that ddt(Phi-in) is initially 0 at time=0. After that, ddt(Phi-in) can correctly represent input frequency. Because Vout is inversely proportional to Fin, i.e., inversely proportional to ddt(Phi-in), it causes Vout infinitely large at the beginning. How to solve this issue?

    2. I can only try to lose the voltage blowup constraint to overcome above issue. But the voltage output is still incorrect. It seems verilog-A cannot handle the inverse of ddt, i.e., 1/ddt(Phi-in) correctly. How to solve this issue?

    Or simply to say, can verilog-A experts help me to correctly express my FVC function in verilog-A?

    Thanks a lot!

Sincerely,

  • Quek

    Hi Teem

    I think it would be best for you to contact your local Cadence support for more help as this question cannot be easily answered without some testing using your codes.

    Best regards
    Quek

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