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Problem with GPDK090: triple well layout

jgmelo

Hello,
  I am using Cadence GPDK090 and having a few problems with isolated NMOS (triple well).
  For test purposes, what I am trying to make is an inverter, in which the NMOS is isolated. If I use the component nmos1v_iso of GPDK090 in the schematic, it simulates just fine. However, when designing the corresponding layout, I add the layout instance nmos1v_iso and de DRC passes, but the LVS complains that I am using the conventional nmos1v component in the layout, not nmos1v_iso. It seems to be a bug.
  The alternative I already tried: I looked in the GPDK090 documentation the layers that compose nmos1v_iso and, starting from the layout cell nmos1v, I built my own triple well. However, DRC stopped me at all my tries.

  I hope you can help me with this issue. If you need me to send additional information and files, please let me know.
 
  Thanks in advance,
 
  João
 

Parents
  • Sorry, I forgot to include the software version.
    ====== Products versions ======

    virtuoso version 6.1.5
    sub-version IC6.1.5.500.11

    spectre version 11.1.0 32bit
    sub-version 11.1.0.576.isr17

    assura version av4.1:Production:dfII6.1.5:IC6.1.5.500.17
    sub-version 4.1_USR4
Reply
  • Sorry, I forgot to include the software version.
    ====== Products versions ======

    virtuoso version 6.1.5
    sub-version IC6.1.5.500.11

    spectre version 11.1.0 32bit
    sub-version 11.1.0.576.isr17

    assura version av4.1:Production:dfII6.1.5:IC6.1.5.500.17
    sub-version 4.1_USR4
Children
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