Hierarchy Editor - How to use library list

Hello,

I am still trying to figure it out how library list is used in hierarchy editor in case of textual views (for example : reference verilog ), If someone can explain the usage of liblist through an example would be great !!

Regards,

Atul Dubey

Dear Atul,

> I am still trying to figure it out how library list is used in
> hierarchy editor in case of textual views (for example : reference
> verilog ),

I am probably not understanding your question - so I must, initially, apologize if I am not help to answer your question! However, the library list indicates those libraries from your cds.lib which the hierarchy edit will search for the name of the cells in your design. If you do not include a library in your list that contains one or more of the cells in your design, the hierarchy editor will indicate that the cell is not found. This will prevent you from creating a netlist of the design. There is no difference in its use if the cell has a "textual" view or a schematic/extracted view. The default view to be used is specified by the order of the views you select and the placement of the stop view in that list. 

I have attached an example of the hierarchy editor where I have circled the library list at the top and how two verily cells are instantiated. Note each cell is from a library in the library list. Their verilog views were selected as the verilog view in the "View List" appears before the "Stop List" view (spectre in this case).

I hope this helps.

Shawn

smlogan said:

There is no difference in its use if the cell has a "textual" view or a schematic/extracted view. The default view to be used is specified by the order of the views you select and the placement of the stop view in that list. 

This bit isn't true. The library list is only needed to resolve instances which do not have a library binding. Schematics always are fully-bound - they have an explicit library and cell specified, so the library list does not affect them, and there is no need to have anything in the library list for schematic-based designs. Verilog is however different, because when you instantiate a module in a Verilog module, you only reference the cell and not the library - the library is "loose". The library list is used to resolve the library in those cases. Consequently, it should only affect instances inside Verilog views (or similar) where the library needs to be identified.

Regards,

Andrew.

Dear Andrew,

I apologize for my error and misunderstanding. I do appreciate you taking the time to clarify the difference in library binding when invoking schematic and verilog views. I hope it helps Etul resolve his issue.

Sorry!

Shawn

Thanks Shawn and Andrew !!

That helps.

Regards,

Atul Dubey

Shawn,

No need to apologise - I really appreciate the help you often give, as what with my day job, answering in the forums is hard to keep up with. So having other folks happy to contribute is fantastic - I hope you're not offended if I make mild corrections here and there (it's the pedant in me...)

Regards,

Andrew.