Questions on Verilog-XL structural schematic bottom-up flow

Our group currently use IC6.1.3 and we plan to upgrade IC6.1.6 in the next month or so. We have a set of novel circuit primitives whose digital behavior is modeled in Verilog. We then create digital circuits by connecting the corresponding symbol views structurally in a schematic using Virtuoso XL. The schematic is then processed by Verilog-XL to create the top-level structural verilog netlist which we then use to simulate the design.

- Is there a better or more modern way to carry out such a flow that I am not aware of (particularly for IC6.1.6)?

- Can SystemVerilog or VHDL-2008 be used? I would like to use some of the more advanced features of these languages to improve the modeling of the logic behavior of the individual circuit primitives.

Thanks in advance.