Standard Cell Substrate Contacts

Hi,

I am currently creating a standard cell library and a few simple circuits from it using Cadence schematics/layout and a 65nm TSMC library.

The DRM states that a well tap need only be included every 15um. Henceforth the standard cells do not include taps, but a separate tap cell is created and included every so often in the designs. The wells are then abutted between cells to provide the substrate/NWell connection to the rails via the tap cells.

Taking a simple example of a single nmos transistor, the corresponding model from the technology file includes the source/drain/gate/substrate connections.

If you create the layout from this, you add pin labels on the metal layers for the source/drain/gate, but what about the substrate connection?

If I run LVS it fails, based on the fact that the schematic includes 4 ports, but the layout only includes three (the ones labelled on the metal layers).

In my design the substrate is connected to ground and the NWell connected to VDD, but because there are no taps included in the cell, the cells themselves fail LVS if I tie the backgate connections to the rails in the schematic.

I do not understand the correct procedure to tell the tools that there is a connection to the backgate as defined in the schematic, but this is not explicitly included in the cells because it is provided somewhere else.

Does anyone know how I do this?