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Error while generating LEF file in Abstract

RAO VINAY

I have designed a cascode LNA and used an on-chip inductor from VDD to output node "OutL". The functionality is verified through post-lyout simulation and also I could generate gds file. However, I am getting following error while after running EXTRACT in abstract.

"Extraction has been aborted because a short has been detected between the nets VDD and outL.
Check the following
1)If you are performing antenna extraction, ensure that "Layer Assignment for Antenna Extraction" table
on the "Antenna" tab has been populated correctly. The geometry specification for the diffusion layer in the table should read
"diff diff and not poly".
2>Ensure that the "Layer connectivity" on the "General" tab is set up correctly for all layers, especially for polysilicon and
metal1 and diffusion and metal1, such as "(ploy metal1 contact) (diff metal1 contact)""

Though it is showing right mark in EXTRACT column, abstract run is not moving beyond 22%. I couldn't understand the error and suggestion given during EXTRACT run. There are no short exist between VDD and outL.  Can any one tell me, how to rectify these errors? In abstract it has passed "pins" perfectly.

Regards,

Vinay Rao.

Parents

  • Hi Rao,

    You say that you are using an on-chip inductor and that there are no shorts between VDD and OutL

    But the tool is finding a short because you got an error message.

    So this indicates that the extractor doesn't have the correct information to extract correctly

    You probably need to define a stopping layer that would normally be drawn over your inductor for such a case.

    You also need correct layer assignments in the power and signal extract forms.

    This would normally be setup by your pdk provider. There is too much to explain in this forum so perhaps you could check the documentation.

    A quick solution could be to simply ignore net OutL for extraction.

    In the extract form, power tab, turn off "extract power nets"

    In the pins form, map tab define "OutL" as a power pin (second field, power pin names)

    That's one way to do it. You should then get a usable abstract.

     

    Colin

     

Reply

  • Hi Rao,

    You say that you are using an on-chip inductor and that there are no shorts between VDD and OutL

    But the tool is finding a short because you got an error message.

    So this indicates that the extractor doesn't have the correct information to extract correctly

    You probably need to define a stopping layer that would normally be drawn over your inductor for such a case.

    You also need correct layer assignments in the power and signal extract forms.

    This would normally be setup by your pdk provider. There is too much to explain in this forum so perhaps you could check the documentation.

    A quick solution could be to simply ignore net OutL for extraction.

    In the extract form, power tab, turn off "extract power nets"

    In the pins form, map tab define "OutL" as a power pin (second field, power pin names)

    That's one way to do it. You should then get a usable abstract.

     

    Colin

     

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