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How to verify custom design efficiently?

dogrush

We are using virtuoso platform to perform full custom design. However, I think it maybe not enough to do the function validation with only he spectre simulations. So, I am wondering whether there are some more efficient approaches to do the validation?

First, I came out the idea to perform nc-verilog simulation by create an function view for nfet and pfet. Then extract the verilog netlist from each schematic, and do the nc-verilog simulation.

But, I guess that there maybe some more efficient approaches to verify the functional correctness and the system performance. Such as, using some tools to obtain the characterization for each cell (schematic or layout), and then using some synthesis tools to evaluate the timing, power, and etc. Just like the encounter to do the physical design with standard cell libraries (that is, we build the standard cell libraries?).

Anyone who knows some design tools or design flow/methodologies for the above approaches? Thanks.

  • Not sure doing a switch level simulation in NC verilog is a particularly good way of doing things (although I have used this approach many years ago with Verilog-XL which had a switch level simulator). Normally you would use models for the digital gates to speed up simulation (i.e. use a Verilog description of the gates). If the circuit isn't digital though, this is not going to help and NC Verilog would not be a good choice.

    Without knowing what type of design you're simulating, or the size of the design, it's hard to give a generic recommendation.

    Kind Regards,

    Andrew.

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