• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. Specifications problem

Stats

  • Locked Locked
  • Replies 0
  • Subscribers 125
  • Views 14724
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Specifications problem

gonsays1
gonsays1 over 10 years ago

Hello,

I've been designing a Two-stage CMOS OTA folded cascode amplifier.

The schematic for the simulation is presented below:

The schematic of the symbol Amplifier2 is presented below:

I must get the following specifications:

  • Small Signal Gain (Av) greater than 70dB;
  • Bandwidth (Bw) greater than 60kHz;
  • Phase Margin (PM) around the value of 60 degrees;
  • Slew-rate (SR) bigger than 200V/us;
  • Current Budget of 400uA (the current used on the circuit must be below 400uA)

I have used the following dimensions for the transistors and values for the DC current sources of the biasing circuits used on the simulation:

  • IBIAS2=125uA;
  • IBIAS=75uA;
  • L=0.55um (I’ve used the same length for all the transistors, I don’t know if this is a good method);
  • W12=11.25um (this value is for the width and width stripe of the transistor M12 – the same logic is applied for the other transistors);
  • W1=W2=50um;
  • W11=27um;
  • W3=W4=W5=W6=W7=W8=13.5um;
  • W9=W10=8.9um;
  • W13=11.25um;
  • W14=55um

Using the values presented before, the specifications of interest obtained by the calculator functions, are the following (and also, some comments of what need to be improved):

  • Av: 70.82dB -> I would need to increase the Small Signal Gain (Av), because it is near the minimum required value of 70dB;
  • SR: 201.5M -> I would need to increase the Slew-Rate (as it is near the minimum value of 200M);

  • Bw: 67.12kHz -> I think the Bandwidth is OK (above the minimum of 60kHz) and can be eventually reduced to increase the Small Signal Gain (Av);

  • PM: 56.83 degrees -> I would need to increase the Phase Margin to a value near 60 degrees;


  • GBW product: 234M -> This value is just to have an idea of the Gain-Bandwidth Product;

  • Current Budget of 400uA is being respected, because the total current used on the circuit is around 320uA (can eventually be increased if needed);

QUESTIONS:

Should I use the same length for all the transistors?

Can you give me a clue regarding the parameters that I should modify in order to get better values for the specifications?

In this case, what is the theoretical expression for the slew-rate?

Thank you very much in advance!

  • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information