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Design of Inductor in CMOS - Help needed

Pyroblast

Hello guys, how you doing?

I want to design an inductor with the lowest resistance as possible. For that I am willing to use and electromagnetic simulator to assess and test the indutor.

The technology that I am using is from UMC 130nm. The maximum width that the tech accepts without introduction of slots is 10um. From 10um to 25um slots must be added. The maximum width that the tech allows is 25um.

Generally speaking, I would like to know what is the methodology to insert slots in the metal tracks? (if there is any) What we have to take into account?

- When inserting the slots, we must check the DRC rules regularly until the error goes away?

- There is any tool that does that? That inserts the necessary number of slots to comply with the DRC rules?

That said, now:

Supposing that I want to design a metal track of 100um: Can I use a very large width of 100um metal and then add slots until the complies with the DRC rules? (if it is done this way)

Or should I use 4 metal tracks of 25um. After that, connect each of them to each other by several other metal tracks in perpendicular. Then add slots and check with the DRC rules tool?

I am looking forward to hear from you.

Kind regards.

Parents
  • Pyroblast

    Hi Andrew and thank you for your reply.

    I understand that the use of multiple metal tracks on top of each other, tied with vias might help reduce the resistance. On the other side, I don't know at what extend it can affect the inductance. Just simulating with a EM tool.

     

    Regarding the slots, what does the possibilities presented do with respect creating the slots? Can you explain how they work? How does work the create -> slot (as well the other solution that you presented). Can you explain briefly?

    Well, it might not exist any tool that do what I want, but regardless this, what is the common practice when we are faced with this problem? To introduce slots in the metal?

    Regards

Reply
  • Pyroblast

    Hi Andrew and thank you for your reply.

    I understand that the use of multiple metal tracks on top of each other, tied with vias might help reduce the resistance. On the other side, I don't know at what extend it can affect the inductance. Just simulating with a EM tool.

     

    Regarding the slots, what does the possibilities presented do with respect creating the slots? Can you explain how they work? How does work the create -> slot (as well the other solution that you presented). Can you explain briefly?

    Well, it might not exist any tool that do what I want, but regardless this, what is the common practice when we are faced with this problem? To introduce slots in the metal?

    Regards

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