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Instantiating Spectre/Spice module inside Systemverilog testbench for irun based flow

rrpat

Hi all

I was trying to  set up irun based test flow for one of our mixed signal design.Here I  have systemverilog testbench and my DUT can be either wreal model /spectre/verilog.So is it possible to have  systemverilog TOP module with wreal/spectre modules instantiated inside  for irun based AMS  flow ?

Btw  I am able to run the simulations using ADE based flow ,but I would like set a simulation flow without using hierarchy editor based net listing. Any leads will be very helpful.

Thanks

  • rrpat
    I found the answer in AMS Designers user guide under section "Using SystemVerilog Modules". Let me try the flow !!! Thanks

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