Problem with importing verilog to Cadence virtuoso

Hi,

I am trying to import a synthesized file.v to cadence to use it as other analog circuits.

I have wrote a verilog logic and synthesized it using YOSYS open source tool. Then I mapped it to a library called cmos_cells.lib using the same tool and I named it: xxx_synth.v.

Well, in reference library: I put basic and cmos10lpe. Those two are already added in my cadence environment libraries.

In verilog file: I put the synthesized file xxx_synth.v

In -v option: I put: cmos_cells.v. This file is part of the tech library that I used to map it in the synthesis tool.

I choose schematic option.

Now, after I import it I got only symbol view. No schematic, gates or transistors.

Please can you help:

1- what is missing?

2- Do I need after synthesizing to map it to a specific library .lib?

3- If I don't have digital library .lib that match the analog library which belong to the same technology, how can I solve it?

Thanks