Stats

  • Locked Locked
  • Replies 1
  • Subscribers 125
  • Views 1015
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Can I use a "not synthesized verilog file" in Cadence Virtuoso?

aamn

Hi,

Can I import a verilog file that is not synthesized and use it as a block in my analog simulation?

  • If you have a Verilog File that is an RTL or behavioural description, then you can't use it in a pure Analog simulation, because it's a digital representation. So that means you can't use it in spectre or other circuit simulators. Spectre understands structural Verilog, but that's just a netlist format which can be used to describe higher level connectivity with gate level transistor level descriptions underneath.

    Spectre also understands Verilog-A (an analog behavioural language).

    However, you can use AMS Designer - this is a mixed-signal simulator which can simulate Verilog, System Verilog, Verilog AMS, VHDL, VHDL AMS, SystemC, etc together with transistor level circuitry. There's no need for the Verilog to be synthesized.

    Regards,

    Andrew.

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.