• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. Model Names In Extraction View

Stats

  • Locked Locked
  • Replies 2
  • Subscribers 125
  • Views 13311
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Model Names In Extraction View

hoodskier
hoodskier over 10 years ago

Hello,

I've designed a chip using Cadence (first time!) and I'm using I/O and supply pads from a pre-defined library that include ESD protection diodes.  The schematic for the diodes has a model name Dpnp or Dnpn depending on the diode (nwell or pwell).  When I extract the layout view for the diode the model named used is either ami06NP or ami06PN.  This creates a problem when I attempt to simulate the extracted view since a model with this name doesn't exist.  How can I define what Cadence will use for a model name for the device when I extract the layout?  Thank you!

-Kevin

  • Cancel
Parents
  • Andrew Beckett
    Andrew Beckett over 10 years ago

    Kevin,

    This rather depends on which LVS and extraction tools you're using. Assuming it's Assura, this is defined in the extract.rul (extraction rules) for Assura. The rule files will have lines like this:

    extractMOS("g45n2svt" _nmos_25 poly_conn("G") ndiff_conn("S" "D")
        pwell("B") spiceModel("g45n2svt") cellView("nmos2v ivpcell gpdk045")
        flagMalformed)
    ...
    extractDIODE("g45nd1svt" _ndio pwell("PLUS") ndiff_conn("MINUS")
        spiceModel("g45nd1svt") cellView("ndio ivpcell gpdk045") flagMalformed)

    Regards,

    Andrew.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • Andrew Beckett
    Andrew Beckett over 10 years ago

    Kevin,

    This rather depends on which LVS and extraction tools you're using. Assuming it's Assura, this is defined in the extract.rul (extraction rules) for Assura. The rule files will have lines like this:

    extractMOS("g45n2svt" _nmos_25 poly_conn("G") ndiff_conn("S" "D")
        pwell("B") spiceModel("g45n2svt") cellView("nmos2v ivpcell gpdk045")
        flagMalformed)
    ...
    extractDIODE("g45nd1svt" _ndio pwell("PLUS") ndiff_conn("MINUS")
        spiceModel("g45nd1svt") cellView("ndio ivpcell gpdk045") flagMalformed)

    Regards,

    Andrew.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information