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Latchup simulation?

Gordon Neue

Hello,

in recent times i have been experimenting a lot with the transistor backgate: translinear circuits, dynamically tuning the treshold, log-domain circuits, subtreshold source coupled logic etc. One of the topics that arises when playing with the backgate is latchup. I am worried that moving the well voltage dynamically could increase the risk of latchup, because i am de-facto injecting charge into a parasitic SCR gate. In modern CMOS processes there are various protection mechanisms against latchup - STI, guard rings, keeping track of the resistance of the well contacts etc, but i am not certain to what degree these protect in this use case. Currently do not have any solid way how verify by simulation, what margin of safety i have in regard to latchup. This is quite unsettling.

Has anyone been in a similar situation? Are there cadence tools to simulate latchup? Is it possible to extract the parasitic thyristor structures from the design and model them? If the foundry does not include the parasitic well BJTs in the device models, is there anything i could still do?  

Process is 180nm CMOS. Cadence 6.1.5-64bit linux.

Thank you,
Best Regards,

Gordon Neue

  • Dear Gordon,

    Since the phenomena associated with latch up requires knowledge of the entire substrate topology and physical parameters (including dopings and their profiles) as well as the temporal behavior of the node voltages, its presence cannot be predicted with certainty using only a circuit simulation. Without a 3D or 2 1/2D process simulation of the specific circuit layout and its environment, the robustness of a circuit to latch up can be studied using a set of foundry DRCs as well as a physical inspection of the layout combined with some knowledge of trace resistances. This does not insure the circuit will not ever exhibit latch up, but can be used in lieu of time consuming 3D process based simulations to increase one's confidence. Companies such as Silvaco provide simulators that can be used to examine latch up for a given circuit topology, If you are interested, they provide an example of their simulators at URL:

    I hope this helps a little Gordon. I am sure there are some experts who can provide more or better information.

    Shawn

  • Hello Shawn, I was hoping i could do this without a TCAD, but i understand. Thank you for the helpful link. We have access to the Silvaco tools in our laboratory, i will probably have to guesstimate the well doping profile.

    Thank you,

    Best Regards,

    Gordon

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