not getting parasitic information inside the extracted netlist created using pvs qrc

In the log file certain layers are not being mapped.

Usually the vendor provided us with Assura QRC deck for extraction so using that we used to perform the extraction. Presently we don't have the same,we have PVS and QRC and here we did like before going to qrc we did lvs using pvs (the rule card provided by the customer is callibre supproted file).we specified svdb directory as the qrc_data  directory.

During the lvs cell.lvsfile was formed inside the svdb directory and the procfile ,p2lvsfile and qrctecfile was already present inside the 65nm tech_dir provided by the customer.

the log file is mentioning like :- 

WARNING (CAPGEN-41242): [input]: Via effect is already described in process file. -add_via_effect is obsolete and will be ignored.

WARNING (CAPGEN-41466): process layer 'Metal7' maps to one or more extraction
layers that do not appear in the lvsfile.

WARNING (CAPGEN-41466): process layer 'MetalMT' maps to one or more extraction
layers that do not appear in the lvsfile.

WARNING (CAPGEN-41466): process layer 'MetalMB' maps to one or more extraction
layers that do not appear in the lvsfile.

WARNING (CAPGEN-41466): process layer 'Metal6' maps to one or more extraction
layers that do not appear in the lvsfile.

WARNING (CAPGEN-41466): process layer 'Metal5' maps to one or more extraction
layers that do not appear in the lvsfile.

WARNING (CAPGEN-41466): process layer 'Metal4' maps to one or more extraction
layers that do not appear in the lvsfile.

WARNING (CAPGEN-41466): process layer 'Metal3' maps to one or more extraction
layers that do not appear in the lvsfile.

WARNING (CAPGEN-41466): process layer 'Metal2' maps to one or more extraction
layers that do not appear in the lvsfile.

WARNING (CAPGEN-41466): process layer 'Metal1' maps to one or more extraction
layers that do not appear in the lvsfile.

WARNING (CAPGEN-41466): process layer 'Poly' maps to one or more extraction
"NFSDA10LACMP.log" 607L, 32566C

ARNING (CAPGEN-41466): process layer 'SD' maps to one or more extraction
layers that do not appear in the lvsfile.

WARNING (CAPGEN-41446): Substrate layer 'SD' will be automatically generated
during extraction due to incomplete p2lvs mapping. This may lead to
unintended results.

WARNING (CAPGEN-41474): Contact layer 'TVAM' specified in the p2lvsfile is not found in the lvsfile.

WARNING (CAPGEN-41474): Contact layer 'TVACB' specified in the p2lvsfile is not found in the lvsfile.

WARNING (CAPGEN-41474): Contact layer 'TVACA' specified in the p2lvsfile is not found in the lvsfile.

WARNING (CAPGEN-41474): Contact layer 'NCA' specified in the p2lvsfile is not found in the lvsfile.

WARNING (CAPGEN-41474): Contact layer 'NAE' specified in the p2lvsfile is not found in the lvsfile.

WARNING (CAPGEN-41474): Contact layer 'NAD' specified in the p2lvsfile is not found in the lvsfile.

WARNING (CAPGEN-41474): Contact layer 'NAC' specified in the p2lvsfile is not found in the lvsfile.

WARNING (CAPGEN-41474): Contact layer 'NAB' specified in the p2lvsfile is not found in the lvsfile.

WARNING (CAPGEN-41474): Contact layer 'NAP' specified in the p2lvsfile is not found in the lvsfile.

WARNING (CAPGEN-41474): Contact layer 'NADF' specified in the p2lvsfile is not found in the lvsfile.

INFO (CAPGEN-41737): Lvs layers DIFF D_0B3B D_0B3C D_0B3E D_0EDIOP EPI MINUS_0MFC MINUS_0MFCAD M_0FUSE M_0LAA M_0LAB M_0LAC M_0LAD M_0LAE M_0LAF M
_0LAG M_0LAH M_0LBA M_0LBB M_0LBC M_0LBD M_0LCA M_0LCB M_0LDA M_0LZA M_0LZB M_0LZC M_0LZD M_0TMA Node_01Minus Node_01Plus Node_0Centor Node_0S PAD
PLUS_0MFC PLUS_0MFCAD POLY are not mapped in layer_setup file

WARNING (RCXSPIC-28081): no via between lyrs 'Metal1' & 'SD'; Via effect ignored. Remove the 2 layers for -add_via_effect

==========================================================#
# Form capacitance layers for non-resistive process layers
#==========================================================#
createEmptyLayer SD
createEmptyLayer Metal7
createEmptyLayer MetalMT
createEmptyLayer MetalMB
createEmptyLayer Metal6
createEmptyLayer Metal5
createEmptyLayer Metal4
createEmptyLayer Metal3
createEmptyLayer Metal2
createEmptyLayer Metal1
createEmptyLayer Poly
#==========================================================#
# Form substrate
#==========================================================#

WARNING (RCXSPIC-27116): There are no non-empty MOS/LDD devices with diffusion layer 'SD' and poly layer 'Poly'. Cannot perform gate capacitance b
locking for user-specified layer 'Gate_EXCAP'.

Only warnings are there but here no parasitic information is generated in the cell.net.Please help and say what went wrong