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  3. IIP3 simulation: shooting vs. hb and choosing extrapolation...

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IIP3 simulation: shooting vs. hb and choosing extrapolation point

itos
itos over 9 years ago

Hi,

I have a simple voltage mode passive mixer (using NMOS transistors) in a 28nm process. I drive the mixer with a port, then an ideal balun, then shunt positive/negative ports with 50 Ohm for matching and connect 100fF at the output node of the mixer.



I follow Lab9 (IP3 Calculation (Swept QPSS and QPAC)) of "SpectreRF Workshop" by Cadence to calculate IIP3. I have some questions on this:

1.) What are typical values from your experience, what can I use as a "best I can get" reference? Is +10dBm great? Or +30dBm?

2.) This is the result of using shooting engine in qpss:





The curve is not monotonic and depending on the extrapolation point I get significantly different results. How can that be? What would be the best value for the extrapolation point in this case? ep=-50 gives 24dBm but ep=-20 would give me >30dBm.

3.) The same simulation but taking harmonic balance instead of shooting:

Now it's even more non-monotonic, and the result differs by 10dB!

Why is the difference so significant and which result should I trust and why?

Thank you!

PS: Good to know because it took me hours to find it out: For these curves to work, the input to port must be in dBm (not V!) and also for PAC value it needs to be the same (contrary to a document by Ken Kundert, where he writes the small signal pac value does not matter)

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  • itos
    itos over 9 years ago

    Hi Andrew, this is great input! Actually I stumbled already across this but forgot it again. There are two other interesting papers discussing this: "The New CMC Standard Compact MOS Model PSP: Advantages for RF Applications" (Scholten et.al.) and "Distortion in Current Commutating Passive CMOS Downconversion Mixers" (Larson et.al.).

    This is probably a stupid question ... but how do I make VDS!=0 without significantly altering the actual circuit? Connect a (big) resistor in parallel (drain to source)? Maybe not, this would increase Ron ...

    Connect an ideal voltage source between source and drain?

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  • itos
    itos over 9 years ago

    Hi Andrew, this is great input! Actually I stumbled already across this but forgot it again. There are two other interesting papers discussing this: "The New CMC Standard Compact MOS Model PSP: Advantages for RF Applications" (Scholten et.al.) and "Distortion in Current Commutating Passive CMOS Downconversion Mixers" (Larson et.al.).

    This is probably a stupid question ... but how do I make VDS!=0 without significantly altering the actual circuit? Connect a (big) resistor in parallel (drain to source)? Maybe not, this would increase Ron ...

    Connect an ideal voltage source between source and drain?

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