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Parasitic extraction of FinFET inverter using planner CMOS rules

skvishvakarma

Hi

I have 15nm free pdk from NCSU and can design inverter layout and also check the design rules.

But I can't extract the parasitic as I don't have LVS and XRC rules file.

Is there any way to extract the parasitics in this situation?

I am thinking to extract the parasitics using old planner MOS rules (65nm, 90, 45 etc), would it be good?

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  • I rather doubt that would work. Unless the LVS rules can recognize the devices and layers used in the PDK, it's not going to be of much use.

    Looking at the NCSU site about this PDK: (that's the release notes), it seems that the LVS and XRC rules are planned for the next release. However, since all the Physical Verification rules are for Calibre (which is a Mentor Graphics product, not a Cadence Design Systems product), this doesn't seem a particularly appropriate forum to ask this question unless you are using a Cadence physical verification tool (you didn't say which tools you were using) and are appealing to find out if somebody has written some rules already for this pseudo-technology.

    Regards,

    Andrew.

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  • I rather doubt that would work. Unless the LVS rules can recognize the devices and layers used in the PDK, it's not going to be of much use.

    Looking at the NCSU site about this PDK: (that's the release notes), it seems that the LVS and XRC rules are planned for the next release. However, since all the Physical Verification rules are for Calibre (which is a Mentor Graphics product, not a Cadence Design Systems product), this doesn't seem a particularly appropriate forum to ask this question unless you are using a Cadence physical verification tool (you didn't say which tools you were using) and are appealing to find out if somebody has written some rules already for this pseudo-technology.

    Regards,

    Andrew.

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