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Parasitic extraction of FinFET inverter using planner CMOS rules

skvishvakarma

Hi

I have 15nm free pdk from NCSU and can design inverter layout and also check the design rules.

But I can't extract the parasitic as I don't have LVS and XRC rules file.

Is there any way to extract the parasitics in this situation?

I am thinking to extract the parasitics using old planner MOS rules (65nm, 90, 45 etc), would it be good?

Parents
  • Thanks. I am using both calibre and asuura for physical verification whenever needed. Till the time of next release from NCSU i wanted to try to find a way to extract the parasitics. As I tried and did'n find written rules, I want to try myself. If you have any kind of information related to the rules written for FinFET for Cadence environment, please let me know.
Reply
  • Thanks. I am using both calibre and asuura for physical verification whenever needed. Till the time of next release from NCSU i wanted to try to find a way to extract the parasitics. As I tried and did'n find written rules, I want to try myself. If you have any kind of information related to the rules written for FinFET for Cadence environment, please let me know.
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