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VerilogIn import of structural/behavioral design

JohnB70

Hi,

I want to use VerilogIn to import a hierarchical behavioral verilog design so that I can simulate with ADE/AMS.

Do I just need to specify the highest level verilog file? Or do I need to specify all files in the design?

If all need to specified, do I keep adding these to the "Verilog Files to Import" field, or can I list them in a file?

Where would I specify this file name.

The designer also uses a variable that sets the size of a register bank. This needs to be predefined before he simulates the verilog and I presume it needs to be predefined for verilog in also. How do I predefine this variable.

Thanks,

John

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  • Andrew Beckett

    John,

    You need to specify all the files you want to import. You can either specify these directly through the UI, or add them in a file and use the -f option on the form. Also in that file you could use -DEFINE to define any preprocessor macros needed (I think that's what you're talking about) - see "ihdl -help" for more info on that, but it follows the same kind of arguments to ncverilog, verilog and irun.

    Regards,

    Andrew

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  • Andrew Beckett

    John,

    You need to specify all the files you want to import. You can either specify these directly through the UI, or add them in a file and use the -f option on the form. Also in that file you could use -DEFINE to define any preprocessor macros needed (I think that's what you're talking about) - see "ihdl -help" for more info on that, but it follows the same kind of arguments to ncverilog, verilog and irun.

    Regards,

    Andrew

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