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Automatically create verilog views

JohnB70

I have a digital standard cell library from the foundry.

Usually there is a symbol, schematic, layout and verilog view for each cell.

However in the latest version the verilog views are missing.

There is a separate folder called verilog where there is a verilog file for each cell.

Is there a way to automatically create the verilog views from this folder?

Without these views I can't specify in the conifig to use the verilog description instead of the transistor-level schematic.

Or is there some other way I can tell ADE/AMS to look in that verilog folder for the verilog descriptions.

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