Swapping in DSPF netlists using the Hierarchy Editor?

Marc,

If you had been using spectre, there's an easy way using Setup->Simulation Files->DSPF ... which tells it to include the DSPF and use the terminals from the schematic block so that means you don't have to worry about pin orders and so on. This isn't available for UltraSim so we need to use a slightly more complicated approach.

First of all, in the hierarchy editor, you can use RMB->Set Cell View->Specify SPICE Source File over the cell you wish to switch to DSPF. Then navigate to the DSPF file you wish to use for the block. 

This will then cause the netlister to stop at that cell, and also add an include statement to include the DSPF.

For this to work, the termOrder in the CDF has to be correct and match the DSPF. There are a couple of ways of achieving this:

1. If using QRC to generate the DSPF, it offers the choice of specifying the pin order for the DSPF. You can copy this from the spectre simulation information in the CDF into the QRC form, and then the DSPF file will have a terminal order that matches the CDF. Of course, it's important that the CDF termOrder is up to date - and you can achieve that by opening the schematic and typing: artGenerateHierSymbolCDF(geGetEditCellView()) in the CIW.
2. Alternatively, use Tools->CDF->Edit CDF, select Base, and pick your cell that you wish to replace with the DSPF. Using the Simulation Information tab, switch to spectre as the simulator, and then update the termOrder field to match the order in the DSPF. Note that the names in this field must be the names on your schematic/symbol, so if there's any discrepancy between the names used in the DSPF and the symbol you'll need to take care of that here (typically this would be bus delimiters). A difference is OK, because spectre/Ultrasim will connect by order, so you just need to ensure that the order of the symbol pin names matches the order of the DSPF pin names.

Having done this, just simulate as normal in UltraSim. No stitching needed. However, be aware that UltraSim's ability to partition will be compromised by doing this - it won't be able to use isomorphism because it's dealing with a flat design. Stitching allows it to use the original hierarchy for isomorphism and partitioning, and then add the parasitics afterwards. Stitching is more complex though and harder to get "complete"...

Regards,

Andrew.

Awesome, thanks! I found the cell in the Hierarchy Editor and set it to use the DSPF. Then I edited the CDF for the cell to have the same terminal names and order as the DSPF. I used the Hierarchy Editor to open the schematic and from the schematic I launched ADE. In ADE, I set the simulator as Ultrasim and created the netlist. In the netlist I don't see anything that indicates the DSPF is being included. Are there any steps in the Hierarchy Editor such as editing the Inherited View List that may need to be done?

Marc,

At the very bottom of the input.ckt file I see:

// UltraSim ADE Specific Options (Not required for standalone simulations)
usim_opt output_upper=0 ade=1 wf_spectre_syntax=1
usim_opt wf_param_hier=1
usim_opt wf_dataset=spectre
// UltraSim Simulator Options
include "/export/home/andrewb/workshops/mmsim141_emir_workshop/ade_mmsim_voltus_workshop/adc_sample_hold.dspf"

The include line is coming from the HED settings. If you don't see this, which IC version are you using?

Can you also see if there are any messages in the CIW about a valid source file being found?

Another thing to check is to type:

hnlSourceFileDisabled

in the CIW. If this has been set to t then it's been disabled for some reason in your environment. You could try setting it to nil and see what happens (you may need to do netlist recreate).

Regards,

Andrew.