AMS netlisting has failed

I am trying to create a AMS netlist, but I got the error message in CIW. (AMS netlisting has failed) There's only one warning message in the netlister log (No error). I am using Virtuoso IC6.1.6-64b.101; INCISIVE 14.20.001

The warning message is as following...

WARNING (VLOGNET-121): You are netlisting with the test fixture flag set to OFF.
This could result in possible timescale directive violations. No timescale directive will be added by the netlister. Set the test fixture option to ON before netlisting if there are such violations.

How to set this "test fixture option" to ON in AMS? I set simVerilogTestFixtureFlag = t in .cdsinit file, but the message remained unchanged.

In "Netlist and Run Options", Mode is "OSS-based netlister with irun"

I tried to set AMS_UNL=YES, but I am not sure if it works since I still get "OSS-based netlister with irun."

The circuit is very simple, it's just an inverter chain (some verilog models & one schematic(spectre)). All the blocks are from the same cell, but different "View To Use" setting in the config (Hierarchy Editor).

Thank you.

CIW info:

INFO (VLOGNET-187): While generating an explicit netlist, it is recommended to set the Terminal SyncUp option on the Netlist Setup form as 'Merge All' with this option. Alternatively, you can set the hnlVerilogTermSyncUp variable as 'mergeAll'. This helps in generating a pure explicit netlist.

INFO (VLOGNET-60): The stimulus name mapped table will not be printed in the "/home/user/cadence/simulation/top/ams/config/netlist/testfixture.verilog" file. To print the stimulus name mapped table, set simVerilogPrintStimulusNameMappingTable = t either in CIW or the .simrc file before invoking Verilog netlister.

INFO (VLOGNET-62): Database internal net names will be printed for floating instance ports. To prevent them from being printed, set simVerilogProcessNullPorts = t either in CIW or the .simrc file.

INFO (VLOGNET-64): All cellviews in the design will be printed in the Netlist Configuration list. If you want to print only those cellviews that need to be re-netlisted in the list, set simVerilogIncrementalNetlistConfigList = t either in CIW or the .simrc file.

INFO (VLOGNET-68): The initial state of stimulus of all inout pins is set to "z". To get inout pins with initial state of "0", set nlVerilogIOInitStimulusStr = "0" either in CIW or the .simrc file.

INFO (VLOGNET-117): Re-netlisting the entire design.

INFO (VLOGNET-118): Using connection by name (explicit connections) for all stopping and non-stopping cells.

WARNING (VLOGNET-121): You are netlisting with the test fixture flag set to OFF. This could result in possible timescale directive violations. No

timescale directive will be added by the netlister. Set the test fixture option to ON before netlisting if there are such violations.

Traverse Config lib: test cell:top view:config

ERROR (AMS-1247): AMS netlisting has failed.

Check Simulation->Output Log->Netlister Log for errors.

Correct your design and netlist again.

...unsuccessful.