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Composer Schematic with Split Bus Naming

ckteng

I've got a complicated wiring situation. I'd like to create a simple expression to capture the following pattern with buses "a" and "b":

b<59>,b<19>,a<59>,a<19>,...,b<41>,b<1>,a<41>,a<1>,b<40>,b<0>,a<40>,a<0>

I can't see a way to have the bus split up like this and have the incrementing pattern. I'd really like to avoid having to write out the bits one-by-one.

There is the repeating operator but that will just repeat the pattern given 20 times.

<*20>(b<40>,b<0>,a<40>,a<0>)

Any ideas? Thanks!

  • Marc,

    I don't think you can create naming syntax for interleaved busses without explicitly naming all the bits. There's a recent CCR asking for such capability, 1492066, so please contact customer support and request a duplicate on your behalf (make sure you list your specific requirement, because it's slightly different from what is discussed in that CCR). It's possible that you might need to add patch cords to alias the two halves of each bus so that the bit ranges are common for all interleaved signals, but knowing your request might mean that if implemented, you scenario could be taken into account in any enhancement.

    Right now, the only way is probably to write some SKILL code to generate the expression to avoid you having to type it:

    for(bit 0 19
       sprintf(expr "b<%d>,b<%d>,a<%d>,a<%d>%s" bit+40 bit bit+40 bit if(bit==0 "" strcat("," expr)))
    )

    The variable expr will contain your expression afterwards.

    Regards,

    Andrew.

  • Thanks! OK, I will look into filing a CCR.

    I was going to write Perl code to generate the net names. I foresee running into a problem because the label name is limited to 1024 characters. I may have hundreds of nets each with lengthy names.

  • You may need to use a patch from basic to alias the names to something shorter to avoid any limitations. I didn't think the name was limited 1024 characters these days though (although it will be a bit cumbersome if it is very long...)

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