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Parameterized Layout Design

skvishvakarma

Hi

I am using Virtuoso 6.1.6-64b.

I have created "Graphical Parameterized Cell" for NMOS/PMOS.

May I use the same method for CMOS inverter and AND/NAND gates? 

I would like to parameterize whole layout of AND/NAND gate (interconnect/contacts/PR all can be parameterized).

I am trying but do not know the way how to proceed?

I tried to compile the AND gate shows the following error in CIW:  

(PC-101002): Compiling Parameterized Cell ...

*Error* fprintf/sprintf: format spec. incompatible with data - "Format is '\n; generate all the primitive shapes in layer \"%s (%s)\"\n', argument #2 is nil"

 

Waiting eagerly for positive response.

Parents

  • Hi Sjoerd,

    See this CDN Live EMEA 2015 presentation and this CDN Live EMEA 2014 presentation. The first talks more about using PCell Designer for module PCells, whereas the second gives a more general overview.

    The idea is that it's a graphical environment for creating pcells which can be used to build object oriented pcells without you necessarily needing to know much (or any) SKILL. You can start with original shapes from the layout editor and then import them into the tool and then operate on these shapes with commands which are similar to those in the layout editor - but adding familiar programming commands for looping, conditionals etc. You can create your own commands within the tool to capture more complex operations. It's pretty hard to summarise here in just a few words - the presentations do a better job, and actually seeing the tool does a better job still. It's not really like the existing graphical pcell tool - it has a different use model from that - but it is more graphical in nature than writing SKILL code. You can make changes interactively and then see immediate feedback on the changes in the layout editor, and has a number of useful debugging aids within the tool.

    If you contact me directly (send me a friend request with your email address in the request) I can discuss this with you and if appropriate arrange a demo.

    Kind Regards,

    Andrew.

Reply

  • Hi Sjoerd,

    See this CDN Live EMEA 2015 presentation and this CDN Live EMEA 2014 presentation. The first talks more about using PCell Designer for module PCells, whereas the second gives a more general overview.

    The idea is that it's a graphical environment for creating pcells which can be used to build object oriented pcells without you necessarily needing to know much (or any) SKILL. You can start with original shapes from the layout editor and then import them into the tool and then operate on these shapes with commands which are similar to those in the layout editor - but adding familiar programming commands for looping, conditionals etc. You can create your own commands within the tool to capture more complex operations. It's pretty hard to summarise here in just a few words - the presentations do a better job, and actually seeing the tool does a better job still. It's not really like the existing graphical pcell tool - it has a different use model from that - but it is more graphical in nature than writing SKILL code. You can make changes interactively and then see immediate feedback on the changes in the layout editor, and has a number of useful debugging aids within the tool.

    If you contact me directly (send me a friend request with your email address in the request) I can discuss this with you and if appropriate arrange a demo.

    Kind Regards,

    Andrew.

Children
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