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Parameterized Layout Design

skvishvakarma over 9 years ago

I am using Virtuoso 6.1.6-64b.

I have created "Graphical Parameterized Cell" for NMOS/PMOS.

May I use the same method for CMOS inverter and AND/NAND gates?

I would like to parameterize whole layout of AND/NAND gate (interconnect/contacts/PR all can be parameterized).

I am trying but do not know the way how to proceed?

I tried to compile the AND gate shows the following error in CIW:

(PC-101002): Compiling Parameterized Cell ...

*Error* fprintf/sprintf: format spec. incompatible with data - "Format is '\n; generate all the primitive shapes in layer \"%s (%s)\"\n', argument #2 is nil"

Waiting eagerly for positive response.

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skvishvakarma over 9 years ago

Hi Andrew

Would you please tell me how can I check whether I already have PCell designer or not and how can I invoke it.
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skvishvakarma over 9 years ago

Hi Andrew

Would you please tell me how can I check whether I already have PCell designer or not and how can I invoke it.
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