how could i handle a dual-path PFD+CP structure when using noise aware PLL flow?

Dear all,

I'm simulating a ring-vco based PLL for clock generation. I want to know the  jitter of the proposed circuit. So I decided to run the noise aware PLL flow to simulate the whole system's jitter performance. But I was stuck at some problems.

1. My PLL is a typical analog PLL, which consists a PFD, a CP, a VCO and a divider and some other bias circuits. For the reason of achieving faster lock, I designed a dual-path PFD+CP structure. Typically, the PFD detects the rising edge or the falling edge of the reference clock and the feedback clock, but my design detects both edges. When running the noise aware PLL flow, I happened to find that the mismatch of the Iup and Idown seems too big, i.e. the Iup is 5uA, while the Idown is -19uA, shown in the output log file. And what's more, the difference between uptr and downtr ,refdelay and fbdelay, are large too.

I tried another PFD+CP stucture, which detects only the rising edge, the mismatch seems negligible.

So my problem is how do I handle the dual-path PFD+CP stucture.

2. I have another question which is what does the period jitter or phase jitter means?

In the noise aware PLL flow, the output' PSD curve contains information like the period jitter=12e-11s, the phase jitter=60e-10s. What does these terms mean? Is there any help file which defines these two terms rigorously? And what's the relationship between these terms and the Jc, Jcc and so on?

Hoping for your reply!

Thanks!