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  3. hysteresis using vcvs

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hysteresis using vcvs

gau27
gau27 over 9 years ago

Hi fellow forum users,

Guess most of you will read this only in the New Year, yet hope someone like me working just before x'mas will take a peek at my issue!

I'm toying with the vcvs PWL transfer char. to simulate a hysteresis comparator.

Sim errors saying I've got infinite slope for the PWL char. Not sure how we implement this.

Appreciate any ideas.

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  • gau27
    gau27 over 9 years ago

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  • Andrew Beckett
    Andrew Beckett over 9 years ago

    Your transfer function appears to have an error in it - I'm assuming input 3 should be avdd/2+Vh/2. Anyway, even with that corrected, this isn't going to work because it requires some kind of "state" to be maintained and the vcvs won't do that - it's a stateless transfer function (i.e. for every input value there's a single output value).

    Your best bet would be to write a VerilogA model. This model on the Designer's Guide site is a good start - it's a Verilog-AMS model and would need to be changed to have a voltage output rather than a logic output, but you get the idea: dg-vams4-14

    Regards,

    Andrew.

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  • gau27
    gau27 over 9 years ago

    Thanks for the quick reply, Andrew.

    Yes, you're right about the  PWL input3 value, good spot!

    I was coding a veriloga model in parallel but still wanted something with ideal components without positive feedback. Anyhow, now I've got one with resistors implementing the hysteresis.

    Thanks & wish you a Merry Christmas

    Gautham

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