• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. Netlisting failed with multiple Verilog-A blocks

Stats

  • Locked Locked
  • Replies 1
  • Subscribers 125
  • Views 16244
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Netlisting failed with multiple Verilog-A blocks

ywyc
ywyc over 9 years ago

Hello,

I have encountered netlist errors when trying to simulate circuit which has two simple Verilog-A blocks. Each individual block can be nestlisted successfully. However when I put them in the same schematic, there are errors. The error messages are:

"ERROR (OSSHNL-524): Netlisting failed as function hnlNetNameOnTerm was called with a non-existent terminal name on current instance 'I1' in design 'RF14/cal_logic_decod/schematic'. Ensure that argument to this function is a valid terminal name and netlist again.\n\n"
and many more of the same thing...

The two verilog-a blocks are defined like

module A(B_in, T_out);

input [4:0] B_in ;
electrical [4:0] B_in ;
output [15:0] T_out ;
electrical [15:0] T_out ;

endmodule

module B(clk, vin, vout);

input vin, clk;
output [4:0] vout;
electrical vin, clk;
electrical [4:0] vout;

endmodule

Please advise, thank you.

  • Cancel
Parents
  • Andrew Beckett
    Andrew Beckett over 9 years ago

    Sounds rather odd. Which version of the IC tools are you using? (Help->About in the CIW will tell you the subversion). Assuming that the symbols match the VerilogA views, it may just be a matter of check-and-save of the schematic containing the two instances. However, I'm guessing. I suspect that (assuming this is in some vaguely recent version of the software, and it isn't fixed in a later version) you will need to contact customer support so that we can actually see the problematic data, as guessing the problem here might be hard as I'm sure it is specific to your data, as nothing you've described here is terribly unusual.

    Regards,

    Andrew.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • Andrew Beckett
    Andrew Beckett over 9 years ago

    Sounds rather odd. Which version of the IC tools are you using? (Help->About in the CIW will tell you the subversion). Assuming that the symbols match the VerilogA views, it may just be a matter of check-and-save of the schematic containing the two instances. However, I'm guessing. I suspect that (assuming this is in some vaguely recent version of the software, and it isn't fixed in a later version) you will need to contact customer support so that we can actually see the problematic data, as guessing the problem here might be hard as I'm sure it is specific to your data, as nothing you've described here is terribly unusual.

    Regards,

    Andrew.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information