Verilog-A 2**integer yields wrong value

Hi,

I have come across a very strange bug. I created a module in verilog-A that at some point converts a integer input into a binary number. To do so it successively divides the input by factors of 2

However, I found that using an expression of type:

2**i // i declared an integer

Does not result in the right number being generated!

Look at the following for loop

        for (i=`NUM_ADC_BITS-1; i>=0; i=i-1 ) begin
            $display("%d", 2**i);
        end

It ouputs:

2048
1024
511
255
127
63
32
15
8
4
2
1

Using a genvar or the function pow() solves the problem, however this behaviour seems to be potentially very dangerous to me. Does anyone have any insight of why this (should) happen?

Many thanks,

Alberto Gomez