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Parametric analysis (in ADE) differs from single analysis, at equal parameter

Clidre
Clidre over 9 years ago

Hello,

I'm facing a problem with spectre. I made a system with ideal components: it's an ideal current source that is directed to a capacitor for some time and then redirected to a low impedance node for another time slot. I use ideal switches to rearrange the circuit. The capacitor is precharged with a voltage, depending on a digital code. In my system there are ideal components from analogLib and digital ports in verilogA. A dc analysis doesn't converge. I'm interested in the overall functioning over time and I managed to simulate it with a tran analysis + skipdc. 

I did a parametric analysis, changing the digital code and I noticed that, for a certain code, the waveforms differ from what I expected. By running the same simulation just once (I set the problematic code in the Design Variables list in ADE), the waveforms are sensibly different from what I get in the parametric analysis at the same code.

I cannot understand why, any suggestions?

Thanks a lot!

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  • Clidre
    Clidre over 9 years ago

    By initializing the verilogA flip-flop output with @(initial_state)  begin x=0; end  , I managed to do the dc simulation and a transient analysis with skipdc=no. Now both the results seem to be consistent: for each parameter, if I run a parametric analysis or a single simulation, I get the same result.

    Any insight would be helpful. Thanks!

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  • Clidre
    Clidre over 9 years ago

    By initializing the verilogA flip-flop output with @(initial_state)  begin x=0; end  , I managed to do the dc simulation and a transient analysis with skipdc=no. Now both the results seem to be consistent: for each parameter, if I run a parametric analysis or a single simulation, I get the same result.

    Any insight would be helpful. Thanks!

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