Stats

  • Locked Locked
  • Replies 1
  • Subscribers 125
  • Views 13126
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Problem after cdb2oa translation

DevB

Dear all,

I have some layouts done in older IC version (5.1.0) which are DRC and LVS passed. Now after translating them to OA for the new version, 6.1.5, I get DRC error ("P+ Diffusion overlap Contact is 0.1um" and "N+ Diffusion overlap Contact is 0.1um"). Upon closer look in the layout, the overlap of S/D area with metal1 in PMOS and NMOS seems distorted (Please see the attached picture). This problem exists even when I try to make a new layout, so there could be a problem with the cdb to oa translated technology library itself.

IC version 6.1.5

Technology library -UMC180nm_MixedModeRFCMOS


Kindly help,

Best regards

Debajit

Parents
  • DevB

    Dear all, 


    The problem in the Pcell was solved by updating the design kit for IC6.


    Regards,

    Debajit

Reply
  • DevB

    Dear all, 


    The problem in the Pcell was solved by updating the design kit for IC6.


    Regards,

    Debajit

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.