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Virtuoso Layout Editor net highlighting

apple419

Hello,

Need some help on Cadence virtuoso layout editor (version 615) net highlighting or marking.

let's say there is a signal that goes to a NMOS gate (poly). At the same time the signal also goes to a poly resistor. The other end of the poly resistor is tied to ground.

Now if I highlight this net it will highlight both the net and the poly resistor. The net is shown to be shorted to the ground through the poly resistor.

In MarkNet Options form I can deselect (POLY2) (CONT) (MET1) and (POLY1) (CONT) (MET1). But the problem is the poly gate of the NMOS will not be highlighted.

So the question is how to differentiate poly gate highlighting from the poly resistor highlighting?

Same question applies to MIM capacitors.  


Thanks for helping!

Parents
  • skillUser

    Look for a 'recognition' layer for the Poly Res and MIM Cap devices, this will allow you to distinguish between the gate poly and resistor poly.

    Hope it helps!

    Lawrence.

Reply
  • skillUser

    Look for a 'recognition' layer for the Poly Res and MIM Cap devices, this will allow you to distinguish between the gate poly and resistor poly.

    Hope it helps!

    Lawrence.

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