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If-else statement in VerilogA- Designing a memory element

Nishtha Sharma

Hello, 

I am trying to design a memory element using VerilogA. In the case where the input voltage goes between +Vtmax and -Vtmax, the code doesn't remember the previous value of x and the control directly jumps to else statement. How can I make it remember the previous value of x? 

  • Andrew Beckett

    It might help if you posted the entire module, not just bits of it. It's hard to see what you've done in the other definitions...

    How are you testing it too? Can you provide a simple netlist too? Everyone on these forums is doing this in their spare time, so minimising the amount of effort we need to expend to understand your problem will make it much more likely that you'll get an answer.

    Kind Regards,

    Andrew.

  • Nishtha Sharma

    Hello Andrew ,

    I fixed the issue. There was a mistake in the output assignment statement. I will attach the updated code here if anyone wants to refer to it.  Thanks!

    Best,

    Nishtha

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