Verilog - AMS model for powerFET

To replace the spice level model with verilog ams at top level to increase the speed  .

idea here is to model powerfet  in verilog ams which should meet atleast following specs:

VDS (V) 40
RDS(on)  at VGS = 10 V 0.0063
RDS(on)  at VGS = 4.5 V 0.0075
ID (A) 58

//Verilog-AMS HDL for "FetModels_lib", "powerFET_sqj858c" "verilogams_1"

`include "constants.vams"
`include "disciplines.vams"

module powerFET_sqj858c ( D, G, S );

//==============================================================================
// Declarations (ports, parameters, variable, wires)
//==============================================================================
inout S, G, D;
electrical S, G, D;


parameter real vth = 2.0 from [0.1:10.0];
// parameter real cgs = 2.0e-9 from [1e-15:1e-6];




// variables/wires/registers
real rds;
real id, id_linear, id_sat ,rds_linear, rds_sat ;

// ===========================================================================

//==============================================================================
// Analog section
//==============================================================================

analog
begin

// when vds << vgs - vth it acts as voltage controlled resistor
//rds_sat = 50/(id_sat) ; // in sat mode the output resistance ro = 1/Id*(lamda) where lamba equals 0.02V^(-1)

//rds = V(D,S)<(V(G,S)- vth) ? rds_linear : rds_sat ;

//I(D, S) <+ V(D, S)/rds;

//I(D, S) <+ V(D, S)/rds ;

@(above(V(G,S)- vth - V(D,S),100p,50m))

begin

id = 2*2*5*( (V(G,S) - vth)*V(D,S) - 0.5*pow(V(D,S),2) ) ;

end

@(above( V(D,S) - V(G,S) + vth ,100p,50m))

begin

id = 2*2*(pow((V(G,S) - vth),2)) ; //(1+0.02*(V(D,S))) ; // drain current equation in saturation mode

end

I(D,S) <+ id ;


end
endmodule