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DRC and LVS body floating problem

Manp

Hi there,

I am working on one SRAM  bitcell and a macro.

I have got a question regarding LVS and DRC errors and the troubleshooting methods.

Tools used in this project:

Virtuoso IC6.1.5-64b.500.132

used Technology: ST65nm

I got to know recently that there is a trick to go around LVS and DRC errors regarding body floating (orCMOS latch-up based on DRC). based on that there exist probably a pin layer (which I don't know the name) which with creating 'vdds' and 'gnds' pin or label using that layer inside PP or NP layer the LVS  doesn't say anything about missing ports and DRC avoids giving LUP.D.1 and LUP.D.2 errors

LAYOUT NAME                                           SOURCE NAME
Discrepancy #2 in bitcell                                                                 
** missing port **                                        vdds on net: vdds
** missing port **                                       gnds on net: gnds

is there anyone who knows this trick and can help me?

Parents
  • Andrew Beckett

    More important than the tool versions would be to know which technology you're using. The rule names will be dependent upon the particular technology you're using - as would the layers and so on. Maybe if you post that, somebody can help you (I can't because I doubt I am familiar with the specific technology in question, and also don't have access to Calibre because it's a tool from Mentor Graphics not Cadence Design Systems).

    Kind Regards,

    Andrew

Reply
  • Andrew Beckett

    More important than the tool versions would be to know which technology you're using. The rule names will be dependent upon the particular technology you're using - as would the layers and so on. Maybe if you post that, somebody can help you (I can't because I doubt I am familiar with the specific technology in question, and also don't have access to Calibre because it's a tool from Mentor Graphics not Cadence Design Systems).

    Kind Regards,

    Andrew

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