Invisible Inherited signals in Verilog-A

Hello all,

I'm trying to develop a model in Verilog-A that will correspond to the same block/function in the schematic level. The schematic block has two inherited signals that define the power pins. I'd like to perform the same function in Verilog-A as well. I have no problem with the coding itself, it works fine no errors or warnings but on the other hand the two inherited signals are visible to the block as two inout ports. You may have a look at the definitions of the signals:

module anyName(clkd, clkd_90, clk, clk_90, icp_5u, hSup, lSup);
output x;
electrical x;
output y;
electrical y;
input z;
electrical z;
input s;
electrical s;
input a;
electrical a;
(* inh_conn_prop_name="lSup",inh_conn_def_value="cds_globals.\\VSS! " *) inout VSS_A;
electrical VSS_A;
(* inh_conn_prop_name="hSup",inh_conn_def_value="cds_globals.\\VDD! " *) inout VDD_A;
electrical VDD_A;

I played with many options/settings in virtuoso but all in vain. If I go and edit the symbol through deleting the two ports, they are no longer accessible. What I want to have at the end is something like this:

Any input is appreciated, 

Sherif