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"Assertion Failed" in Noise-Aware PLL Simulation

Cod Liang

Dear all,

I’ve followed the tutorial of Noise-Aware PLL Design Flow released by Cadence and try to get the phase noise of my PLL.

The VCO+DIVIDER macro model extraction went well with no error. (please see http://imgur.com/WabXwrT)

However, when I moved to PFD+CP extraction, “assertion failed” popped out and the simulation was ceased. (please see http://imgur.com/6DjFyLS, http://imgur.com/Hr9TP7N, http://imgur.com/uRqrS50)

I was almost sure that the instance name and cell name of the port in these testbenches were correct, and PSS/Pnoise setup seemed to be nothing different from that shown in the tutorial.

Could anyone please help me figure out the problem?

 

Simulation environment:

Virtuoso version IC6.1.5-64b.500.15

Spectre version 10.1.1 32bit

MMSIM version 10.11.412

 

If the information I provided is not sufficient enough to clarify the problem, please tell me.

Thanks a lot. :)

 

Liang

Parents
  • Cod Liang
    Hi Andrew, thanks for your reply. Actually I had tried to send this error message to Cadence customer support before posting on this community. However I've found it difficult to do this because I didn't have the account to get in. (It requires a Host ID in License Server but I have no permission to get into our License Server.) As a result I could do nothing but post it on this forum to seek for some luck. Anyway I'll try to update simulators and run it again. Is there any updated flow like Noise-Aware PLL which could assist me on estimating PLL phase noise? Really appreciate your answers. :) Liang
Reply
  • Cod Liang
    Hi Andrew, thanks for your reply. Actually I had tried to send this error message to Cadence customer support before posting on this community. However I've found it difficult to do this because I didn't have the account to get in. (It requires a Host ID in License Server but I have no permission to get into our License Server.) As a result I could do nothing but post it on this forum to seek for some luck. Anyway I'll try to update simulators and run it again. Is there any updated flow like Noise-Aware PLL which could assist me on estimating PLL phase noise? Really appreciate your answers. :) Liang
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