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"Assertion Failed" in Noise-Aware PLL Simulation

Cod Liang

Dear all,

I’ve followed the tutorial of Noise-Aware PLL Design Flow released by Cadence and try to get the phase noise of my PLL.

The VCO+DIVIDER macro model extraction went well with no error. (please see http://imgur.com/WabXwrT)

However, when I moved to PFD+CP extraction, “assertion failed” popped out and the simulation was ceased. (please see http://imgur.com/6DjFyLS, http://imgur.com/Hr9TP7N, http://imgur.com/uRqrS50)

I was almost sure that the instance name and cell name of the port in these testbenches were correct, and PSS/Pnoise setup seemed to be nothing different from that shown in the tutorial.

Could anyone please help me figure out the problem?

 

Simulation environment:

Virtuoso version IC6.1.5-64b.500.15

Spectre version 10.1.1 32bit

MMSIM version 10.11.412

 

If the information I provided is not sufficient enough to clarify the problem, please tell me.

Thanks a lot. :)

 

Liang

Parents
  • Andrew Beckett
    On the support site, there's Resources->Rapid Adoption Kits, and then Custom IC and Signoff. Under that, there's a PLL Verification Workshop which covers using a phase--domain modelling approach. However, to get to this, you'll need to sort out the account. Presumably can ask whoever runs the license server in your company, or if you're a University you can look at Support and Training->Cadence University Program at the top of this page to find out how to access support.
Reply
  • Andrew Beckett
    On the support site, there's Resources->Rapid Adoption Kits, and then Custom IC and Signoff. Under that, there's a PLL Verification Workshop which covers using a phase--domain modelling approach. However, to get to this, you'll need to sort out the account. Presumably can ask whoever runs the license server in your company, or if you're a University you can look at Support and Training->Cadence University Program at the top of this page to find out how to access support.
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