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Naming a net with repetitively with same net name in schematic?

nvyayla

Hi,

I have 30+ bits for one of my pin and I need to run simulation for this cell in schematic. I don't have setbitx cells and I am not sure verilog-a can handle this large number(more than 32bit). So what I am trying to do is that I give VSS to 0V and VDD to 1V with vdc. Is there a way to write VSS and VDD like an array for the net name? For instance, for first 5 LSB bits, I want 0 and the rest 1  i.e 11111111111....1100000. I don't want to write VDD,VDD,VDD.....,VDD,VSS,VSS,VSS,VSS,VSS,VSS to net name for this case. Is there a way write VSS, VDD repetitively? I am open to other suggestions if you have any.

Thanks,

yayla

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