To calculate the length of the wire in cadence

Andrew,

I know QRC or EAD can get parasitic resistance of wires but is there any SKILL function or procedure could do it in a more efficient way? Say I have >500  wires at top level and I'd like to do a batch check on those with >1000ohm wire resistance in one day. No need to be fully automated, but at least a more efficient way than check it one by one ....

I'd appreciate you could share some experience on this.

Thanks,

QS

I doubt it. EAD is a net-based fast extractor, so you can extract just the nets you're interested in, to the level of hierarchy you're interested in. 

You could of course write your own extractor, but it's going to be very hard to make it as fast as something that has been optimised to be a fast incremental net-based extractor that doesn't require the layout to be complete...

Regards,

Andrew.

Andrew,

Thanks for the feedback. I understand probably it is very difficult for EAD. How about QRC extracted data? There is "Parasitic" plugin on schematic editor and you can setup a R extracted view then report "terminal-to-terminal" parasitic resistor. This suits my need but it cannot do in a batch way if hundreds of top level nets need to checked. Is there any SKILL function associated with this I can use? Thanks!

Best regards,

QS

I didn't say that it was difficult for EAD - quite the opposite. I said EAD was well suited for this task. The "I doubt it was in response to your question about whether there is a SKILL function that could do this more efficiently.

QRC really requires you to have a layout that is LVS clean, and for you to extract the entire layout (yes, there are options to extract only a sub-set of nets, but it effectively has to do a lot of the work regardless, and just not output all the parasitics). EAD on the other hand requires the design to have been done in a Layout XL compliant way, but doesn't require the layout to be complete, and can really extract just the nets you select.

Regards,

Andrew