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How can I set bus's direction in spicein?

gaojun

Hi,

I'm using spicein to import cdl netlist in virtuoso 6.1.6. It work well for non bus type IO. But if the IO pin in subckt definitation is bus type, for example input<2:0>, and whether I use *.pininfo input:i or *.pininfo input<2:0>:i or *.pininfo input<2>:i input<1>:i input<0>:i, the schematic could not give this pin the correct direction. How can I fix it?

  • Andrew Beckett

    Can you post exactly what the .subckt line (and .pininfo) lines look like? You can't have a bus pin called input<2:0> in SPICE (SPICE only supports single-bit, or scalar, pins) - so I'd like to understand precisely what your example looks like before trying to answer this.

    Regards,

    Andrew.

  • gaojun
    The netlist format is CDL. It looks like: .subckt mycdltop input1<1:0> input2 input3<1:0> output1<1:0> output2 output3<1:0> \n *.pininfo input1<1:0>:i input2:i input3<1:0>:i output1<1:0>:o output2 output3<1:0> \n x0 input1<0> input2 input3<0> output1<0> output2 output3<0> myinstance \n x1 input1<1> input2 input3<1> output1<1> output2 output3<1> \n .ends .subckt myinstance \n .ends
  • Andrew Beckett

    That is not a valid CDL netlist. The definition of CDL is covered in various places in the Cadence documentation, including the Cadence PVS Developers Guide.

    The pins of a SUBCKT must follow SPICE conventions of being single-bit.

    Regards,

    Andrew.

  • gaojun
    Thanks for your explanation. In fact, if the CDL use input<1> input<0> as its port, the symbol generated will use input<1> input<0> as pin individually, and if the CDL use input<1:0> , the symbol will use input<1:0>. For CDL netlist with a lot of multi bit pins, the last symbol seems pretty than previous one. But unfortunately the pin direction is wrong.
  • Andrew Beckett

    Yes, but you're relying on a side-effect. It's not legal CDL - all that's happening is that SPICE IN is just taking the pin-name as is, and because it's a bus, it then happens to work. I suspect that the *.PININFO doesn't work because this is unexpected syntax and the colon in the middle of the pin name is confusing it (you have a colon in the name, and as the separator for the pin direction).

    The alternative would be to use this CDL syntax:

    .SUBCKT myblock a b c b1<2:0> / d e f1<3:0>

    Everything before the "/" is an output pin; everything after is an input pin. This works - I tested it. You're still relying on a side-effect of incorrect CDL syntax, but it does happen to work. The "/" is part of the CDL definition to separate outputs from inputs, and if my memory is correct, predates the introduction of *.PININFO which came at a later date (although that's been there for more than 20 years, I'm sure).

    Regards,

    Andrew

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