XStream and terminals with net expressions

I'm trying to understand some details about how net expressions are handled in various parts of the custom IC flow.  Here is the scenario:

mycell - lower level block with input pin "IN", output pin "OUT" and also on the schematic is a pin with attached net expression.  The pin is "VDD_PIN" with property name "VDD" and default net "vdd!".  Similarly there is a pin "VSS_PIN" with property name "VSS" and default net "vss!".  Then I use "create cellview from cellview" to generate the symbol and I also end up with these two pins that have an attached net expression.  So far so good.   When I instantiate "mycell" into a larger schematic "topcell" I can either draw explicit wires to the power/ground pins or add netSet properties.  All is good, spectre netlists for simulation all look correct.

Then I generate the layout using Layout XL and "generate all from source".  I have the pins set to put the pin on  METAL2/drawing and add an associated text display on <same as pin>/pin for the layer/purpose.  The pins come in.  When I query a pin I see the terminal name and pin name are "VDD_PIN" and under the connectivity tab there is a net expression with property VDD and default net vdd!  The text shows [VDD:%:vdd!].  If I happen to copy that pin to have two pins for the same terminal then my second one is identical except the pin name is different (but of course the terminal name and net expression are the same).  All is good, I'm happy so far.

Where I start to run into issues is both on CDL out and stream out.  It appears that in the stream file, the text which had something like "[VDD:%:vdd!]" got replaced by "VDD_PIN".  Is this behavior documented somewhere?  Are there XStream settings which affect how that text was evaluated?  I looked in the Design Data Translator's Reference and didn't see anything. 

On CDL out, by default I get *.GLOBAL vdd! vss! and *.PINS vdd! vss! and then in my .subckt definition for "mycell" I see "vdd!" and "vss!" used everwhere.  While it seems fairly reasonable (mycell has not been instantiated and therefore we get the default nets in the net expressions), this does not match what is in the stream file for the labels.  So now a verification tool like Calibre will say "oh, you have a port called VDD_PIN in layout and one called vdd! in schematic.  ERROR!" 

I can work around this by using constructs like

LAYOUT RENAME TEXT "/VDD_PIN/vdd!/g" "/VSS_PIN/vss!/g"

in my calibre input.  However, anytime I'm pushed to use a layout rename text I'm worried that sooner or later I'll have a name collision and it will be a Bad Thing.  Is there a way to tell XStream if you prefer the evaluated net name (i.e. the default net or "vdd!" and "vss!") to be used versus the terminal name?  Or perhaps also an option to preserve the net expression?  Or maybe there is no way to represent this in gds2.  As a related thing, I've yet to find a combination of settings that would let me stream out the layout and stream it back in where I preserve net expressions on the pins.  Is there a setting which would do this or is this in the realm of needing to write skill code that digs into the schematic or symbol view looking for terminals and net expressions and repairs pins on a streamed in layout?

Thanks

-Dan