Stats

  • Locked Locked
  • Replies 2
  • Subscribers 125
  • Views 17787
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Deep NWell for NMOS is connected to VSS, how to connect the floating substrate

afridimcci

Hello everyone,

I have designed a circuit which has deep nwell NMOS devices so that the NMOS is isolated from the rest of the substrate. The NMOS body is connected to "VSS". Now the problem is how to connect the floating global p-substrate surrounding the circuit to a different ground node and how to name it so that it clears DRC and LVS checks. I have tried connecting it to a different ground pin but the ERC shows that the psub is still floating.

  • Andrew Beckett

    Given that this is a rather technology-specific question, it would help considerably to know what technology you're using! Maybe somebody who is familiar with that process, the rules, and how the physical verification is set up will then be able to help you.

    Similarly, it would be rather important to know what physical verification tool you're using.

    Kindest Regards,

    Andrew

  • afridimcci

    Hi Andrew,

    It is TSMC 130nm pdk and I am using Calibre LVS for verification. 

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.