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Help with Verilog-A file operation tasks

Reks

Hi, 

I need some help with using the verilog-A file operation tasks.  I am trying to create a subset table from a main table using $fwrite. And then I am trying to fetch some data (Value) from the newly created subset table within the same code. However, when I run this code, it gives me the error: " ERROR! *pvaE* table_model file "./subset.tbl" not found ". If I am not trying to fetch data from the subset table, then the simulation runs without error and the subset table gets created. Looks like the file is getting created only at the end of simulation. My aim is to create a subset table and fetch some data from the subset table within the same code. Could someone help me in correcting the error in the below code. Is there another way to do this??

Below is a snippet of my code:

******************************************************************************************************************************************

module test(p,n);
electrical p,n;
branch (p,n) test;

parameter real Vw=1.5;
parameter real Tmp = 30;

integer fp;
real Vin[1:10] = {0,1,2,3,4,5,6,7,8,9};

analog begin

@(initial_step)

begin

fp = $fopen("subset.tbl");

for(i=1;i<=10;i++)

begin

$fwrite(fp,"%2d\t%1.1f\t%1.1f\t%2.6f \n", Tmp,Vw,Vin[i],$table_model(Tmp, Vw, Vin[i], "./main.tbl", "L,L"));

end

$fclose(fp);

Value = $table_model(Tmp, Vw, Vw, "./subset.tbl", "L,L");

end

end

endmodule

*********************************************************************************************************************************

Parents
  • Andrew Beckett

    I don't know which simulator you're using, but given the errors in the code above, I'm sure it's not spectre and I don't think it's a Cadence simulator (maybe it's PSPICE - not really my area of tool support - however, from a google search I think it's probably HSPICE; if it's HSPICE, then asking this in a Cadence forum rather than a Synopsys forum doesn't make sense. Why do people ask questions without even mentioning which tool they're using?)

    (the form of the error message doesn't look like one of course). For example, you didn't declare i, Value, and the %2d in the $fwrite doesn't make sense since Tmp is a real number. I had to correct these to get it to even run at all (Spectre doesn't like the i++ in the for loop either, needs i=i+1).

    Anyway, according to the Verilog-AMS Language Reference manual, the data source is read at the first call to $table_model - it may be optimised to be at the very beginning of the simulation (that's what seems to happen in spectre, and presumably in whatever simulator you're using). I think in theory $table_model should support reading from arrays rather than a file (and these arrays can be initialised in the initial_step) - Spectre supports this (although I didn't put together an example using this because I didn't have time), and it's in the LRM.

    Regards,

    Andrew.

Reply
  • Andrew Beckett

    I don't know which simulator you're using, but given the errors in the code above, I'm sure it's not spectre and I don't think it's a Cadence simulator (maybe it's PSPICE - not really my area of tool support - however, from a google search I think it's probably HSPICE; if it's HSPICE, then asking this in a Cadence forum rather than a Synopsys forum doesn't make sense. Why do people ask questions without even mentioning which tool they're using?)

    (the form of the error message doesn't look like one of course). For example, you didn't declare i, Value, and the %2d in the $fwrite doesn't make sense since Tmp is a real number. I had to correct these to get it to even run at all (Spectre doesn't like the i++ in the for loop either, needs i=i+1).

    Anyway, according to the Verilog-AMS Language Reference manual, the data source is read at the first call to $table_model - it may be optimised to be at the very beginning of the simulation (that's what seems to happen in spectre, and presumably in whatever simulator you're using). I think in theory $table_model should support reading from arrays rather than a file (and these arrays can be initialised in the initial_step) - Spectre supports this (although I didn't put together an example using this because I didn't have time), and it's in the LRM.

    Regards,

    Andrew.

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