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error during creating the netlist from layout using 45nm technolgy

vinod joshi

Dear Sir/Madam,

We tried to generate the the netlist from ocean script but it showed a blank window without any signal. The error reported in log window has been mentioned below.

/home/student/simulation/inverter2/spectre/layout/psf.

generate netlist...
Loading seCore.cxt
Begin Incremental Netlisting Apr 29 16:40:41 2016
ERROR (OSSHNL-108): The property, 'connectivityLastUpdated', specified on library 'APF_test', cell 'inverter2',
view 'layout', does not have an integer value. Re-extract the design (File->Check and Save menu option) to correct this error.
End netlisting Apr 29 16:40:41 2016
ERROR (OSSHNL-514): Netlist generation failed because of the errors reported above. The netlist might not have been generated at all or,if a netlist was produced, it might be corrupt.Fix the reported errors and generate the netlist again.
...unsuccessful.

with regards,

Vinod

  • Hi Vinod,

    I think this block must have been migrated from an older version (IC5141) and probably has a datestamp based check of whether the connectivity is out of date. Normally that should have been taken care of during migration, so it's a bit odd - I'm wondering whether some SKILL code has been used to artificially update the connectivity status and it's doing it the wrong way.

    So try doing check-and-save on inverter2 and see if that fixes it.

    Regards,

    Andrew.

  • in reply to Andrew Beckett

    Hi Andrew,

    Even I have the same issue, I have copied my standard cell library from one location to another and now it's giving me this error when I run LVS. I can't do check and save on schematics as it's standard cell library. Can you please help me to fix this? I'm using  virtuoso version 6.1.7

  • in reply to rish87

    OK, looking back at what I said then, something was a bit strange - I clearly didn't notice that it was a layout view being spoken about (it's a bit odd trying to netlist the layout view).

    If you're getting the error on the standard cell schematics, you really need to do the check operation on the schematics otherwise it won't be possible to netlist them. You might be able to workaround the problem by opening the schematics in read only mode and using Schematic XL (from the Launch menu) and then you can "check" (on the Check menu) a readonly design. You'd then have to create the netlist (a CDL netlist) for LVS by running the CDL netlister in foreground rather than background (since you didn't save it). 

    So all of this is a bit clunky, requires a schematic XL license, and messing around with how the netlisting is done. It would be far simpler to just open the standard cell schematics in edit mode and do a check-and-save.

    Regards,

    Andrew.

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