How to parameterize a string parameter in ADE XL?

Hi All,

In my verilog-A module foo.va, I have a parameter file_name, like this:

parameter string file_name = "./file.dat";

In my test bench, I have this verilog-A instance foo, and I want to parameterize this parameter file_name by giving it a name "fName", like this:

In ADE XL Test Editor, I tried to "Copy from Cellview". But nothing appeared in the "Design Variable" table.

Now I'm thinking: Can I manually add this variable "fName"? I did and I supplied a valid value to it. The simulation failed and I looked into the file input.scs. It turned out the simulator treats the variable name "fName" ITSELF as a string. Could anybody tell me how to bypass this and let the simulator treat fName as a variable name? Thank you very much!