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What's the difference between gate level extraction and transistor level extraction in Calibre xRC tool.

Biasing

Is there any fundamental difference between gate level extraction and transistor level extraction?

And in calibre xRC toolkit, what does C and CC represent for ?C means the parasitic to the substrate? and CC means the parasitic to the nets?

Best regards,

Mingliang 

Parents

  • Mingliang,

    You might want to look at the logo at the top of this page - it shows "Cadence". Look for the logos you see when using Calibre - you'll see they say "Mentor Graphics". Different company - Cadence's physical verification tools are PVS, Assura, Dracula, Diva (plus a couple of others) - Calibre is not our tool and so this is not really the best place to ask about a tool from a different company!

    However, your questions are pretty generic. Gate level extraction just means that you treat the gates (standard cells) as black boxes and extract the parasitics for the interconnect; often this is done from a DEF description of the layout. Transistor level extraction would be combined with LVS and would extract the devices and all the parasitics around the devices too as well as the interconnect.

    In Calibre terminology, C means lumping the capacitance to ground, whereas CC means extracting the coupled capacitance between nets. You end up with more capacitors that way and it can be slower to simulate because you have a more dense matrix to be solved as there are more interactions to be solved.

    This is all answered without real knowledge of Calibre though - I don't have access to it as an employee of a competing EDA company!

    Regards,

    Andrew.

Reply

  • Mingliang,

    You might want to look at the logo at the top of this page - it shows "Cadence". Look for the logos you see when using Calibre - you'll see they say "Mentor Graphics". Different company - Cadence's physical verification tools are PVS, Assura, Dracula, Diva (plus a couple of others) - Calibre is not our tool and so this is not really the best place to ask about a tool from a different company!

    However, your questions are pretty generic. Gate level extraction just means that you treat the gates (standard cells) as black boxes and extract the parasitics for the interconnect; often this is done from a DEF description of the layout. Transistor level extraction would be combined with LVS and would extract the devices and all the parasitics around the devices too as well as the interconnect.

    In Calibre terminology, C means lumping the capacitance to ground, whereas CC means extracting the coupled capacitance between nets. You end up with more capacitors that way and it can be slower to simulate because you have a more dense matrix to be solved as there are more interactions to be solved.

    This is all answered without real knowledge of Calibre though - I don't have access to it as an employee of a competing EDA company!

    Regards,

    Andrew.

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