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Post Layout Simulation Error

sdineshkumar

Hello Andrew

I am trying to run Post Layout Simualtion for a NOT gate after extracting parasitic capacitances and resistances. The NOT gate was designed using gpdk 45nm technology file.  The RC extraction was done using Assura QRC. Below are the errors while trying to run post layout simulation.

How can i solve this issue

Thank you

Dinesh Kumar

Parents
  • Andrew Beckett

    On the Netlisting tab, you must have these set:

    Please make sure these are set to "do not include" or "include as comment". It's useful to have a model (for the resistors) if you explicitly have provided models for each parasitic resistor (one per layer) - this would allow (for example) layer-specific temperature coefficients to be included in simulation. However, most of the time those models aren't available (and they aren't with gpdk045, so if you wanted that you'd have to write them yourself) so the normal setting (which I think is the default) is to have these set to "do not include" which means it will netlist as a simple resistor or capacitor.

    Regards,

    Andrew.

Reply
  • Andrew Beckett

    On the Netlisting tab, you must have these set:

    Please make sure these are set to "do not include" or "include as comment". It's useful to have a model (for the resistors) if you explicitly have provided models for each parasitic resistor (one per layer) - this would allow (for example) layer-specific temperature coefficients to be included in simulation. However, most of the time those models aren't available (and they aren't with gpdk045, so if you wanted that you'd have to write them yourself) so the normal setting (which I think is the default) is to have these set to "do not include" which means it will netlist as a simple resistor or capacitor.

    Regards,

    Andrew.

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