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Issues with pin connectivity in Layout

DavideP

Hi,

I am working on a design using Virtuoso IC6.1.6.500, and I am having some trouble with pin connectivity on a cell.

My cell layout is basically arranged in a rectangle with a GND strap in the middle, and two VDD straps at top and bottom. I want to place two VDD pins in the layout rather than connecting them together. Looking at the documentation ("Using Connectivity" section of the Layout L user guide), it seems what I need is to create a "must connect" pin group.

I have tried creating a second VDD pin and then following the instructions provided in the user guide ("Using Connectivity" -> "Defining Must Connect Pins"), but this method seems to change the pin's net from VDD to (e.g.) mustConnect_1_VDD. I then get a marker on the pin stating: "Warning: Illegal Must-Join Connection between a pin figure (a rectangle on 'metal1 drawing' on net 'mustConnect_1_VDD') of terminal 'mustConnect_1_VDD' and a rectangle on 'metal1 drawing' on net 'VDD'."

Additionally, LVS complains about having an open circuit on VDD, that the top level port name VDD has already been used on another net, and that there is one extra net and one extra pin compared to the schematic (which has only one VDD pin and net), with some devices being connected to the "wrong" net.

I then found a thread on the forum (community.cadence.com/.../1321872 and tried the solution posted there. Now LVS no longer complains about a top level port name being already used, as that solution says to give the terminal a different name, but I still get the "illegal must-join" marker and all other LVS errors.

Is what I am trying to get (two layout pins corresponding to a single schematic pin/net) doable? If so, does anyone have a suggestion about what I am doing wrong? Or do I need to go back to the schematic and create two VDD1 and VDD2 nets with separate pins and everything?

Parents
  • DavideP

    Hi Andrew,

    First off, apologies for any missing info. I only have started recently to use Virtuoso, so I'm still learning a number of things about it.

    > It's correct that the terminal would be renamed (and the net)

    I see the net change only on the pin properties, but not on other objects that are connected to it. Is that the correct behavior?

    > Also, which subversion of Virtuoso are you using?

    getVersion returns: sub-version  IC6.1.6-64b.500.8

    I tried running your code. What I get is the following:

    abPinInfo()
    TERM db:0x1611db9a NAME "nI0" MUSTJOIN nil PHYSONLY nil
    PIN db:0x26d1b29a NAME "nI0"
    LAYER ("metal1" "drawing") CENTER (10.85 10.01)
    TERM db:0x1611db9b NAME "nI1" MUSTJOIN nil PHYSONLY nil
    PIN db:0x26d1b29b NAME "nI1"
    LAYER ("metal1" "drawing") CENTER (10.26 10.36)
    TERM db:0x1611db9c NAME "nI2" MUSTJOIN nil PHYSONLY nil
    PIN db:0x26d1b29c NAME "nI2"
    LAYER ("metal1" "drawing") CENTER (8.68 10.36)
    TERM db:0x1611db9d NAME "nI3" MUSTJOIN nil PHYSONLY nil
    PIN db:0x26d1b29d NAME "nI3"
    LAYER ("metal1" "drawing") CENTER (7.1 10.36)
    TERM db:0x1611db9e NAME "nI4" MUSTJOIN nil PHYSONLY nil
    PIN db:0x26d1b29e NAME "nI4"
    LAYER ("metal1" "drawing") CENTER (5.52 10.36)
    TERM db:0x1611db9f NAME "nI5" MUSTJOIN nil PHYSONLY nil
    PIN db:0x26d1b29f NAME "nI5"
    LAYER ("metal1" "drawing") CENTER (3.94 10.36)
    TERM db:0x1611dba0 NAME "nI6" MUSTJOIN nil PHYSONLY nil
    PIN db:0x26d1b2a0 NAME "nI6"
    LAYER ("metal1" "drawing") CENTER (2.36 10.36)
    TERM db:0x1611dba1 NAME "nI7" MUSTJOIN nil PHYSONLY nil
    PIN db:0x26d1b2a1 NAME "nI7"
    LAYER ("metal1" "drawing") CENTER (0.78 10.36)
    TERM db:0x1611dba2 NAME "nOUT0" MUSTJOIN nil PHYSONLY nil
    PIN db:0x26d1b2a2 NAME "nOUT0"
    LAYER ("metal1" "drawing") CENTER (14.39 7.7)
    TERM db:0x1611dba3 NAME "nOUT1" MUSTJOIN nil PHYSONLY nil
    PIN db:0x26d1b2a3 NAME "nOUT1"
    LAYER ("metal1" "drawing") CENTER (12.99 7.7)
    TERM db:0x1611dba4 NAME "nOUT2" MUSTJOIN nil PHYSONLY nil
    PIN db:0x26d1b2a4 NAME "nOUT2"
    LAYER ("metal1" "drawing") CENTER (12.35 7.7)
    TERM db:0x1611dba5 NAME "GND" MUSTJOIN nil PHYSONLY nil
    PIN db:0x26d1b2a5 NAME "P__11"
    LAYER ("metal1" "drawing") CENTER (7.49 4.07)
    TERM db:0x1611dba6 NAME "mustConnect_1_VDD" MUSTJOIN (db:0x1611dba7) PHYSONLY nil
    PIN db:0x26d1b2a7 NAME "P__13"
    LAYER ("metal1" "drawing") CENTER (15.1 1.515)
    TERM db:0x1611dba7 NAME "VDD" MUSTJOIN (db:0x1611dba6) PHYSONLY nil
    PIN db:0x26d1b2a6 NAME "P__12"
    LAYER ("metal1" "drawing") CENTER (0.12 11.695)
    t

    > You didn't mention which LVS tool you're using.

    We are using Calibre v2013.1_14.11 . Also, I went through the LVS options after reading your comment about colons, and there is indeed an option to virtually connect pins with a common prefix followed by a colon.

    So, I tried calling the two pins VDD:0 and VDD:1, setting them as must connect, and enabling the virtual connect option on Calibre. If I do that, the LVS report comes out with no errors; however, I get short-circuit markers between the pins and the other objects (says there is a short between e.g. VDD and VDD:0).

    More importantly, if I then place the symbol of the cell I'm creating in a new schematic and try to make a layout of it, the connection to the VDD pin on the schematic no longer carries through to the layout. (That is, on the layout, if I start a path from the VDD:0 pin and then check its properties, the net name property is blank)

    Thanks for your help,

    Dave

Reply
  • DavideP

    Hi Andrew,

    First off, apologies for any missing info. I only have started recently to use Virtuoso, so I'm still learning a number of things about it.

    > It's correct that the terminal would be renamed (and the net)

    I see the net change only on the pin properties, but not on other objects that are connected to it. Is that the correct behavior?

    > Also, which subversion of Virtuoso are you using?

    getVersion returns: sub-version  IC6.1.6-64b.500.8

    I tried running your code. What I get is the following:

    abPinInfo()
    TERM db:0x1611db9a NAME "nI0" MUSTJOIN nil PHYSONLY nil
    PIN db:0x26d1b29a NAME "nI0"
    LAYER ("metal1" "drawing") CENTER (10.85 10.01)
    TERM db:0x1611db9b NAME "nI1" MUSTJOIN nil PHYSONLY nil
    PIN db:0x26d1b29b NAME "nI1"
    LAYER ("metal1" "drawing") CENTER (10.26 10.36)
    TERM db:0x1611db9c NAME "nI2" MUSTJOIN nil PHYSONLY nil
    PIN db:0x26d1b29c NAME "nI2"
    LAYER ("metal1" "drawing") CENTER (8.68 10.36)
    TERM db:0x1611db9d NAME "nI3" MUSTJOIN nil PHYSONLY nil
    PIN db:0x26d1b29d NAME "nI3"
    LAYER ("metal1" "drawing") CENTER (7.1 10.36)
    TERM db:0x1611db9e NAME "nI4" MUSTJOIN nil PHYSONLY nil
    PIN db:0x26d1b29e NAME "nI4"
    LAYER ("metal1" "drawing") CENTER (5.52 10.36)
    TERM db:0x1611db9f NAME "nI5" MUSTJOIN nil PHYSONLY nil
    PIN db:0x26d1b29f NAME "nI5"
    LAYER ("metal1" "drawing") CENTER (3.94 10.36)
    TERM db:0x1611dba0 NAME "nI6" MUSTJOIN nil PHYSONLY nil
    PIN db:0x26d1b2a0 NAME "nI6"
    LAYER ("metal1" "drawing") CENTER (2.36 10.36)
    TERM db:0x1611dba1 NAME "nI7" MUSTJOIN nil PHYSONLY nil
    PIN db:0x26d1b2a1 NAME "nI7"
    LAYER ("metal1" "drawing") CENTER (0.78 10.36)
    TERM db:0x1611dba2 NAME "nOUT0" MUSTJOIN nil PHYSONLY nil
    PIN db:0x26d1b2a2 NAME "nOUT0"
    LAYER ("metal1" "drawing") CENTER (14.39 7.7)
    TERM db:0x1611dba3 NAME "nOUT1" MUSTJOIN nil PHYSONLY nil
    PIN db:0x26d1b2a3 NAME "nOUT1"
    LAYER ("metal1" "drawing") CENTER (12.99 7.7)
    TERM db:0x1611dba4 NAME "nOUT2" MUSTJOIN nil PHYSONLY nil
    PIN db:0x26d1b2a4 NAME "nOUT2"
    LAYER ("metal1" "drawing") CENTER (12.35 7.7)
    TERM db:0x1611dba5 NAME "GND" MUSTJOIN nil PHYSONLY nil
    PIN db:0x26d1b2a5 NAME "P__11"
    LAYER ("metal1" "drawing") CENTER (7.49 4.07)
    TERM db:0x1611dba6 NAME "mustConnect_1_VDD" MUSTJOIN (db:0x1611dba7) PHYSONLY nil
    PIN db:0x26d1b2a7 NAME "P__13"
    LAYER ("metal1" "drawing") CENTER (15.1 1.515)
    TERM db:0x1611dba7 NAME "VDD" MUSTJOIN (db:0x1611dba6) PHYSONLY nil
    PIN db:0x26d1b2a6 NAME "P__12"
    LAYER ("metal1" "drawing") CENTER (0.12 11.695)
    t

    > You didn't mention which LVS tool you're using.

    We are using Calibre v2013.1_14.11 . Also, I went through the LVS options after reading your comment about colons, and there is indeed an option to virtually connect pins with a common prefix followed by a colon.

    So, I tried calling the two pins VDD:0 and VDD:1, setting them as must connect, and enabling the virtual connect option on Calibre. If I do that, the LVS report comes out with no errors; however, I get short-circuit markers between the pins and the other objects (says there is a short between e.g. VDD and VDD:0).

    More importantly, if I then place the symbol of the cell I'm creating in a new schematic and try to make a layout of it, the connection to the VDD pin on the schematic no longer carries through to the layout. (That is, on the layout, if I start a path from the VDD:0 pin and then check its properties, the net name property is blank)

    Thanks for your help,

    Dave

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