A divide by zero exception in connect_lib

Hello,

I am converting my pure schematic and verilogA testbench into the AMS testbench. There is no digital component yet. Here is the ie card spec: 

// This is the Cadence AMS Designer(R) analog simulation control file.
// Generated 'ie' card statement for the Connect Rules.
// TIME : May 17 10:30:09 2016
// IC subversion:  IC6.1.6-64b.500.14
// IUS version: 15.20-s004

amsd{
    ie vsup=0.7 discipline=logic tr=(10p)
}

When the transient simulation does the IC analysis, it spits out a lot of ASL-6236 warnings:

    WARNING (ASL-6236):
        "Incisive//v15.20.002/tools/affirma_ams/etc/connect_lib/Bidir_2.vams"
        180:
        TB.DUT.VDDH1__Bidir_2__logic._cds_internal_Bidir_2_:
        A divide by zero exception has occurred. Therefore, zero will be
        replaced with a small non-zero value of 1e-5.

    WARNING (ASL-6236):
        "Incisive/v15.20.002/tools/affirma_ams/etc/connect_lib/L2E_2.vams"
        153:
        TB.outp__L2E_2__logic._cds_internal_L2E_2_:
        A divide by zero exception has occurred. Therefore, zero will be
        replaced with a small non-zero value of 1e-5.

The offensive lines in both Incisive/v15.20.004/tools.lnx86/affirma_ams/etc/connect_lib/Bidir_2.vam and v15.20.004/tools.lnx86/affirma_ams/etc/connect_lib/L2E_2.vams are:

 analog begin
  rout = transition(Rout,tdelay,tr,tf,ttol_t);     // rout shifts linearly also;
  I(Aout) <+ (V(Aout)-transition(Vstate,tdelay,tr,tf,ttol_t))/rout;    // <<== divide by zero
  highzState = transition($dyn_highz(Aout, enable_highz), 0, tr, tf);
 end

I tried setting the tr=(100p) in the ie card and the warnings still exist. My first question is does anyone know how I can fix these warnings? My second question is why are these connection modules still used even if I do not have any digital verilog/vhdl/ams component in my testbench although I am using the ams simulator.

Thanks,

TJ